1. Technical Field
Exemplary embodiments of the invention relate to a semiconductor integrated circuit device and, more particularly, to a sense amplifier structure of a semiconductor integrated circuit device.
2. Related Art
Dynamic random access memories (DRAMs) are typical semiconductor memory devices that use sense amplifiers to amplify data stored in memory cells. The sense amplifier is configured to connect to a bit line pair (bit line and bit line bar) connected to the memory cells and compare a charge-shared voltage level in the bit line pair with a bit line precharging voltage to discriminate the data of the memory cells.
A conventional sense amplifier includes a latch block, an equalization block, and a column selection block.
The latch block may be disposed between the bit line and the bit line bar and configured to connect PMOS transistors and NMOS transistors in a latch circuit. The equalization block is disposed between the bit line and the bit line bar and serves to make the bit line and the bit line bar to be equipotential in response to an equalization signal. The column selection block may be configured to switch the bit line and the bit line bar to a data transfer line in response to a column selection signal.
The latch block, equalization/precharge block, and column selection block all may be constituted of MOS transistors and gates, where sources and drains of the MOS transistors are appropriately coupled by metal interconnections to have the sense amplifier structure.
However, as the integration density in the semiconductor memory devices increases, distance between active regions becomes largely reduced, and line width of a metal interconnection and distance between metal interconnections are rapidly reduced.
Thus, RC delay of the metal interconnection is increased and coupling between adjacent metal interconnections makes it difficult to accurately transfer signals.